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03.03.2008— Aldec Launches Powerful Verilog Design Rule Checker
Aldec, Inc. announced the world-wide release of ALINTTM , a stand-alone Verilog design rule checker that complies with the second edition of the STARC "RTL Design Style Guide for Verilog HDL".Więcej 
25.02.2008— Aldec Releases Riviera-PRO™ 2008.02 with VHDL 2007, SystemC™ 2.2 and SystemVerilog (DPI)
Aldec, Inc. announced today the release of Riviera-PRO 2008.02, a mixed language HDL simulator that now includes VHDL 2007, integrated SystemC™ 2.2 compiler and SystemVerilog DPI support.
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ALDEC Verification
Methodology Seminars
The new fourth series in the Aldec Verification Methodology Solution (AVMS)
series.
Więcej
13.06-08.06.2008— 45th DAC
The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions. Więcej
Aldec
General Survey — Zachęcamy do wypełnienia
ankiety.
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